mdp5_mdss          12 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c #define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
mdp5_mdss          31 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
mdp5_mdss          33 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	msm_writel(data, mdp5_mdss->mmio + reg);
mdp5_mdss          36 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
mdp5_mdss          38 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	return msm_readl(mdp5_mdss->mmio + reg);
mdp5_mdss          43 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = arg;
mdp5_mdss          46 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
mdp5_mdss          54 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 				mdp5_mdss->irqcontroller.domain, hwirq));
mdp5_mdss          74 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
mdp5_mdss          77 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	clear_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
mdp5_mdss          83 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
mdp5_mdss          86 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	set_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
mdp5_mdss          99 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = d->host_data;
mdp5_mdss         105 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	irq_set_chip_data(irq, mdp5_mdss);
mdp5_mdss         116 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
mdp5_mdss         118 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct device *dev = mdp5_mdss->base.dev->dev;
mdp5_mdss         122 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 				  mdp5_mdss);
mdp5_mdss         128 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.enabled_mask = 0;
mdp5_mdss         129 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.domain = d;
mdp5_mdss         136 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(mdss);
mdp5_mdss         139 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	clk_prepare_enable(mdp5_mdss->ahb_clk);
mdp5_mdss         140 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (mdp5_mdss->axi_clk)
mdp5_mdss         141 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		clk_prepare_enable(mdp5_mdss->axi_clk);
mdp5_mdss         142 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (mdp5_mdss->vsync_clk)
mdp5_mdss         143 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		clk_prepare_enable(mdp5_mdss->vsync_clk);
mdp5_mdss         150 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(mdss);
mdp5_mdss         153 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (mdp5_mdss->vsync_clk)
mdp5_mdss         154 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		clk_disable_unprepare(mdp5_mdss->vsync_clk);
mdp5_mdss         155 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (mdp5_mdss->axi_clk)
mdp5_mdss         156 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		clk_disable_unprepare(mdp5_mdss->axi_clk);
mdp5_mdss         157 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	clk_disable_unprepare(mdp5_mdss->ahb_clk);
mdp5_mdss         162 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static int msm_mdss_get_clocks(struct mdp5_mdss *mdp5_mdss)
mdp5_mdss         165 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 			to_platform_device(mdp5_mdss->base.dev->dev);
mdp5_mdss         167 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->ahb_clk = msm_clk_get(pdev, "iface");
mdp5_mdss         168 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->ahb_clk))
mdp5_mdss         169 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		mdp5_mdss->ahb_clk = NULL;
mdp5_mdss         171 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->axi_clk = msm_clk_get(pdev, "bus");
mdp5_mdss         172 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->axi_clk))
mdp5_mdss         173 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		mdp5_mdss->axi_clk = NULL;
mdp5_mdss         175 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->vsync_clk = msm_clk_get(pdev, "vsync");
mdp5_mdss         176 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->vsync_clk))
mdp5_mdss         177 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		mdp5_mdss->vsync_clk = NULL;
mdp5_mdss         185 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(priv->mdss);
mdp5_mdss         187 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (!mdp5_mdss)
mdp5_mdss         190 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	irq_domain_remove(mdp5_mdss->irqcontroller.domain);
mdp5_mdss         191 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.domain = NULL;
mdp5_mdss         193 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	regulator_disable(mdp5_mdss->vdd);
mdp5_mdss         208 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	struct mdp5_mdss *mdp5_mdss;
mdp5_mdss         216 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss = devm_kzalloc(dev->dev, sizeof(*mdp5_mdss), GFP_KERNEL);
mdp5_mdss         217 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (!mdp5_mdss) {
mdp5_mdss         222 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->base.dev = dev;
mdp5_mdss         224 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");
mdp5_mdss         225 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->mmio)) {
mdp5_mdss         226 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		ret = PTR_ERR(mdp5_mdss->mmio);
mdp5_mdss         230 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
mdp5_mdss         231 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->vbif)) {
mdp5_mdss         232 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		ret = PTR_ERR(mdp5_mdss->vbif);
mdp5_mdss         236 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	ret = msm_mdss_get_clocks(mdp5_mdss);
mdp5_mdss         243 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->vdd = devm_regulator_get(dev->dev, "vdd");
mdp5_mdss         244 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	if (IS_ERR(mdp5_mdss->vdd)) {
mdp5_mdss         245 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 		ret = PTR_ERR(mdp5_mdss->vdd);
mdp5_mdss         249 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	ret = regulator_enable(mdp5_mdss->vdd);
mdp5_mdss         257 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 			       mdss_irq, 0, "mdss_isr", mdp5_mdss);
mdp5_mdss         263 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	ret = mdss_irq_domain_init(mdp5_mdss);
mdp5_mdss         269 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->base.funcs = &mdss_funcs;
mdp5_mdss         270 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	priv->mdss = &mdp5_mdss->base;
mdp5_mdss         276 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	regulator_disable(mdp5_mdss->vdd);