mdp5_kms 777 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, mdp5_kms 780 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 110 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h struct mdp5_kms; mdp5_kms 121 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, mdp5_kms 11 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c static struct mdp5_kms *get_kms(struct drm_encoder *encoder) mdp5_kms 42 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 49 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) { mdp5_kms 61 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE); mdp5_kms 73 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); mdp5_kms 74 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, mdp5_kms 76 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, mdp5_kms 78 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); mdp5_kms 79 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); mdp5_kms 80 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), mdp5_kms 89 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 94 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c ret = clk_set_rate(mdp5_kms->vsync_clk, mdp5_kms 95 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE)); mdp5_kms 101 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c ret = clk_prepare_enable(mdp5_kms->vsync_clk); mdp5_kms 108 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1); mdp5_kms 115 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 119 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0); mdp5_kms 120 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c clk_disable_unprepare(mdp5_kms->vsync_clk); mdp5_kms 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_kms *mdp5_kms; mdp5_kms 187 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_kms = get_kms(encoder); mdp5_kms 203 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c dev = &mdp5_kms->pdev->dev; mdp5_kms 207 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); mdp5_kms 209 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, mdp5_kms 211 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_kms 67 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static struct mdp5_kms *get_kms(struct drm_crtc *crtc) mdp5_kms 165 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); mdp5_kms 166 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct msm_kms *kms = &mdp5_kms->base.base; mdp5_kms 215 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 235 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 331 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, mdp5_kms 333 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, mdp5_kms 335 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, mdp5_kms 338 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, mdp5_kms 340 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, mdp5_kms 342 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, mdp5_kms 347 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); mdp5_kms 348 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), mdp5_kms 351 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); mdp5_kms 352 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), mdp5_kms 366 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 386 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), mdp5_kms 391 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); mdp5_kms 393 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); mdp5_kms 398 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), mdp5_kms 403 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); mdp5_kms 405 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); mdp5_kms 416 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 417 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 429 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); mdp5_kms 431 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); mdp5_kms 436 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags); mdp5_kms 439 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags); mdp5_kms 462 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 463 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 497 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); mdp5_kms 500 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); mdp5_kms 613 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 651 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 792 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 832 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); mdp5_kms 833 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), mdp5_kms 835 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), mdp5_kms 838 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), mdp5_kms 841 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), mdp5_kms 844 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm), mdp5_kms 847 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), mdp5_kms 852 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); mdp5_kms 863 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 864 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct platform_device *pdev = mdp5_kms->pdev; mdp5_kms 865 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct msm_kms *kms = &mdp5_kms->base.base; mdp5_kms 944 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 973 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c pm_runtime_get_sync(&mdp5_kms->pdev->dev); mdp5_kms 981 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c pm_runtime_put_sync(&mdp5_kms->pdev->dev); mdp5_kms 992 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(state->crtc); mdp5_kms 1003 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) mdp5_kms 1156 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(crtc); mdp5_kms 1159 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_update(&mdp5_kms->base); mdp5_kms 75 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_kms *get_kms(struct mdp5_ctl_manager *ctl_mgr) mdp5_kms 85 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); mdp5_kms 88 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, reg, data); mdp5_kms 94 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); mdp5_kms 97 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c return mdp5_read(mdp5_kms, reg); mdp5_kms 100 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void set_display_intf(struct mdp5_kms *mdp5_kms, mdp5_kms 106 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c spin_lock_irqsave(&mdp5_kms->resource_lock, flags); mdp5_kms 107 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); mdp5_kms 131 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); mdp5_kms 132 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); mdp5_kms 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); mdp5_kms 175 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c set_display_intf(mdp5_kms, intf); mdp5_kms 587 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr); mdp5_kms 596 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0); mdp5_kms 609 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, mdp5_kms 13 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c static struct mdp5_kms *get_kms(struct drm_encoder *encoder) mdp5_kms 98 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 167 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), mdp5_kms 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); mdp5_kms 171 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); mdp5_kms 172 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), mdp5_kms 175 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); mdp5_kms 176 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); mdp5_kms 177 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); mdp5_kms 178 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); mdp5_kms 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew); mdp5_kms 180 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol); mdp5_kms 181 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf), mdp5_kms 184 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0); mdp5_kms 185 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0); mdp5_kms 186 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format); mdp5_kms 187 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */ mdp5_kms 197 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 211 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0); mdp5_kms 223 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf)); mdp5_kms 233 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 245 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1); mdp5_kms 328 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 331 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf)); mdp5_kms 337 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms = get_kms(encoder); mdp5_kms 340 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf)); mdp5_kms 348 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_kms *mdp5_kms; mdp5_kms 356 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_kms = get_kms(encoder); mdp5_kms 369 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c dev = &mdp5_kms->pdev->dev; mdp5_kms 374 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); mdp5_kms 375 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); mdp5_kms 376 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_kms 25 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler); mdp5_kms 32 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev); mdp5_kms 33 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c drm_state_dump(mdp5_kms->dev, &p); mdp5_kms 34 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c if (mdp5_kms->smp) mdp5_kms 35 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_smp_dump(mdp5_kms->smp, &p); mdp5_kms 41 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 42 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 45 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); mdp5_kms 46 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_kms 53 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); mdp5_kms 54 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 55 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp_irq *error_handler = &mdp5_kms->error_handler; mdp5_kms 72 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 73 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 76 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_kms 83 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); mdp5_kms 84 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 89 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN); mdp5_kms 90 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable; mdp5_kms 91 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status); mdp5_kms 106 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 107 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 119 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 120 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 28 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 29 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 58 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c spin_lock_irqsave(&mdp5_kms->resource_lock, flags); mdp5_kms 59 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); mdp5_kms 60 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); mdp5_kms 62 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_ctlm_hw_reset(mdp5_kms->ctlm); mdp5_kms 77 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) mdp5_kms 79 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c return to_mdp5_global_state(mdp5_kms->glob_state.state); mdp5_kms 89 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); mdp5_kms 93 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); mdp5_kms 97 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); mdp5_kms 131 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) mdp5_kms 135 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c drm_modeset_lock_init(&mdp5_kms->glob_state_lock); mdp5_kms 141 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c state->mdp5_kms = mdp5_kms; mdp5_kms 143 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, mdp5_kms 151 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 152 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c pm_runtime_get_sync(&mdp5_kms->pdev->dev); mdp5_kms 157 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 158 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c pm_runtime_put_sync(&mdp5_kms->pdev->dev); mdp5_kms 163 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 166 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c global_state = mdp5_get_existing_global_state(mdp5_kms); mdp5_kms 168 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->smp) mdp5_kms 169 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); mdp5_kms 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 182 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) mdp5_kms 188 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 191 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c global_state = mdp5_get_existing_global_state(mdp5_kms); mdp5_kms 193 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->smp) mdp5_kms 194 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); mdp5_kms 225 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 229 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for (i = 0; i < mdp5_kms->num_hwmixers; i++) mdp5_kms 230 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); mdp5_kms 232 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for (i = 0; i < mdp5_kms->num_hwpipes; i++) mdp5_kms 233 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); mdp5_kms 248 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); mdp5_kms 251 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (!mdp5_kms->smp) { mdp5_kms 256 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_smp_dump(mdp5_kms->smp, &p); mdp5_kms 310 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c int mdp5_disable(struct mdp5_kms *mdp5_kms) mdp5_kms 314 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->enable_count--; mdp5_kms 315 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c WARN_ON(mdp5_kms->enable_count < 0); mdp5_kms 317 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_disable_unprepare(mdp5_kms->ahb_clk); mdp5_kms 318 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_disable_unprepare(mdp5_kms->axi_clk); mdp5_kms 319 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_disable_unprepare(mdp5_kms->core_clk); mdp5_kms 320 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->lut_clk) mdp5_kms 321 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_disable_unprepare(mdp5_kms->lut_clk); mdp5_kms 326 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c int mdp5_enable(struct mdp5_kms *mdp5_kms) mdp5_kms 330 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->enable_count++; mdp5_kms 332 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_prepare_enable(mdp5_kms->ahb_clk); mdp5_kms 333 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_prepare_enable(mdp5_kms->axi_clk); mdp5_kms 334 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_prepare_enable(mdp5_kms->core_clk); mdp5_kms 335 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->lut_clk) mdp5_kms 336 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_prepare_enable(mdp5_kms->lut_clk); mdp5_kms 341 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, mdp5_kms 345 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 378 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int modeset_init_intf(struct mdp5_kms *mdp5_kms, mdp5_kms 381 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 383 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; mdp5_kms 399 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c encoder = construct_encoder(mdp5_kms, intf, ctl); mdp5_kms 417 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c encoder = construct_encoder(mdp5_kms, intf, ctl); mdp5_kms 428 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 447 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c encoder = construct_encoder(mdp5_kms, intf, ctl); mdp5_kms 465 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int modeset_init(struct mdp5_kms *mdp5_kms) mdp5_kms 467 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 475 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 481 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for (i = 0; i < mdp5_kms->num_intfs; i++) { mdp5_kms 482 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); mdp5_kms 492 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); mdp5_kms 499 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for (i = 0; i < mdp5_kms->num_hwpipes; i++) { mdp5_kms 500 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; mdp5_kms 553 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, mdp5_kms 556 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct device *dev = &mdp5_kms->pdev->dev; mdp5_kms 560 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); mdp5_kms 682 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms; mdp5_kms 694 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_kms 696 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp_kms_init(&mdp5_kms->base, &kms_funcs); mdp5_kms 698 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c pdev = mdp5_kms->pdev; mdp5_kms 709 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c config = mdp5_cfg_get_config(mdp5_kms->cfg); mdp5_kms 720 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); mdp5_kms 722 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); mdp5_kms 755 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = modeset_init(mdp5_kms); mdp5_kms 781 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); mdp5_kms 784 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->ctlm) mdp5_kms 785 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_ctlm_destroy(mdp5_kms->ctlm); mdp5_kms 786 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->smp) mdp5_kms 787 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_smp_destroy(mdp5_kms->smp); mdp5_kms 788 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->cfg) mdp5_kms 789 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_cfg_destroy(mdp5_kms->cfg); mdp5_kms 791 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c for (i = 0; i < mdp5_kms->num_intfs; i++) mdp5_kms 792 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c kfree(mdp5_kms->intfs[i]); mdp5_kms 794 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->rpm_enabled) mdp5_kms 797 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c drm_atomic_private_obj_fini(&mdp5_kms->glob_state); mdp5_kms 798 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); mdp5_kms 801 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, mdp5_kms 805 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 818 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hwpipe->idx = mdp5_kms->num_hwpipes; mdp5_kms 819 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; mdp5_kms 825 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int hwpipe_init(struct mdp5_kms *mdp5_kms) mdp5_kms 842 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 845 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, mdp5_kms 851 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, mdp5_kms 857 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, mdp5_kms 863 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, mdp5_kms 872 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int hwmixer_init(struct mdp5_kms *mdp5_kms) mdp5_kms 874 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 878 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 891 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mixer->idx = mdp5_kms->num_hwmixers; mdp5_kms 892 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; mdp5_kms 898 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int interface_init(struct mdp5_kms *mdp5_kms) mdp5_kms 900 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 905 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); mdp5_kms 923 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c intf->idx = mdp5_kms->num_intfs; mdp5_kms 924 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; mdp5_kms 933 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms; mdp5_kms 938 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); mdp5_kms 939 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (!mdp5_kms) { mdp5_kms 944 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c platform_set_drvdata(pdev, mdp5_kms); mdp5_kms 946 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c spin_lock_init(&mdp5_kms->resource_lock); mdp5_kms 948 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->dev = dev; mdp5_kms 949 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->pdev = pdev; mdp5_kms 951 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = mdp5_global_obj_init(mdp5_kms); mdp5_kms 955 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); mdp5_kms 956 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (IS_ERR(mdp5_kms->mmio)) { mdp5_kms 957 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = PTR_ERR(mdp5_kms->mmio); mdp5_kms 962 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); mdp5_kms 965 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); mdp5_kms 968 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); mdp5_kms 971 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); mdp5_kms 976 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); mdp5_kms 982 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_set_rate(mdp5_kms->core_clk, 200000000); mdp5_kms 985 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->rpm_enabled = true; mdp5_kms 987 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c read_mdp_hw_revision(mdp5_kms, &major, &minor); mdp5_kms 989 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); mdp5_kms 990 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (IS_ERR(mdp5_kms->cfg)) { mdp5_kms 991 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = PTR_ERR(mdp5_kms->cfg); mdp5_kms 992 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->cfg = NULL; mdp5_kms 996 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c config = mdp5_cfg_get_config(mdp5_kms->cfg); mdp5_kms 997 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->caps = config->hw->mdp.caps; mdp5_kms 1000 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); mdp5_kms 1007 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (mdp5_kms->caps & MDP_CAP_SMP) { mdp5_kms 1008 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); mdp5_kms 1009 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (IS_ERR(mdp5_kms->smp)) { mdp5_kms 1010 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = PTR_ERR(mdp5_kms->smp); mdp5_kms 1011 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->smp = NULL; mdp5_kms 1016 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); mdp5_kms 1017 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c if (IS_ERR(mdp5_kms->ctlm)) { mdp5_kms 1018 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = PTR_ERR(mdp5_kms->ctlm); mdp5_kms 1019 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp5_kms->ctlm = NULL; mdp5_kms 1023 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = hwpipe_init(mdp5_kms); mdp5_kms 1027 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = hwmixer_init(mdp5_kms); mdp5_kms 1031 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c ret = interface_init(mdp5_kms); mdp5_kms 1036 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c priv->kms = &mdp5_kms->base.base; mdp5_kms 1120 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); mdp5_kms 1124 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c return mdp5_disable(mdp5_kms); mdp5_kms 1130 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); mdp5_kms 1134 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c return mdp5_enable(mdp5_kms); mdp5_kms 70 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) mdp5_kms 80 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp5_kms *mdp5_kms; mdp5_kms 87 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms); mdp5_kms 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) mdp5_kms 172 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h WARN_ON(mdp5_kms->enable_count <= 0); mdp5_kms 173 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h msm_writel(data, mdp5_kms->mmio + reg); mdp5_kms 176 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) mdp5_kms 178 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h WARN_ON(mdp5_kms->enable_count <= 0); mdp5_kms 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h return msm_readl(mdp5_kms->mmio + reg); mdp5_kms 270 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms); mdp5_kms 271 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms); mdp5_kms 19 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c static int get_right_pair_idx(struct mdp5_kms *mdp5_kms, int lm) mdp5_kms 28 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c for (i = 0; i < mdp5_kms->num_hwmixers; i++) { mdp5_kms 29 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c struct mdp5_hw_mixer *mixer = mdp5_kms->hwmixers[i]; mdp5_kms 43 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); mdp5_kms 53 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c for (i = 0; i < mdp5_kms->num_hwmixers; i++) { mdp5_kms 54 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i]; mdp5_kms 74 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c pair_idx = get_right_pair_idx(mdp5_kms, cur->lm); mdp5_kms 81 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c *r_mixer = mdp5_kms->hwmixers[pair_idx]; mdp5_kms 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); mdp5_kms 25 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c old_global_state = mdp5_get_existing_global_state(mdp5_kms); mdp5_kms 30 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c for (i = 0; i < mdp5_kms->num_hwpipes; i++) { mdp5_kms 31 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c struct mdp5_hw_pipe *cur = mdp5_kms->hwpipes[i]; mdp5_kms 64 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c for (j = i + 1; j < mdp5_kms->num_hwpipes; mdp5_kms 67 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c mdp5_kms->hwpipes[j]; mdp5_kms 94 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c if (mdp5_kms->smp) { mdp5_kms 101 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c ret = mdp5_smp_assign(mdp5_kms->smp, &new_global_state->smp, mdp5_kms 125 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); mdp5_kms 138 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c if (mdp5_kms->smp) { mdp5_kms 140 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c mdp5_smp_release(mdp5_kms->smp, &state->smp, hwpipe->pipe); mdp5_kms 26 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static struct mdp5_kms *get_kms(struct drm_plane *plane) mdp5_kms 160 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(state->plane); mdp5_kms 164 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) mdp5_kms 242 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(plane); mdp5_kms 243 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_kms *kms = &mdp5_kms->base.base; mdp5_kms 310 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(plane); mdp5_kms 348 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (mdp5_kms->smp) { mdp5_kms 352 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, mdp5_kms 534 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void set_scanout_locked(struct mdp5_kms *mdp5_kms, mdp5_kms 538 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_kms *kms = &mdp5_kms->base.base; mdp5_kms 540 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), mdp5_kms 544 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), mdp5_kms 548 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), mdp5_kms 550 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), mdp5_kms 552 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), mdp5_kms 554 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), mdp5_kms 559 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) mdp5_kms 561 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & mdp5_kms 564 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); mdp5_kms 568 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, mdp5_kms 582 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); mdp5_kms 585 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), mdp5_kms 588 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), mdp5_kms 591 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), mdp5_kms 594 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), mdp5_kms 597 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), mdp5_kms 604 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), mdp5_kms 608 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), mdp5_kms 612 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), mdp5_kms 615 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), mdp5_kms 650 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(plane); mdp5_kms 651 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct device *dev = mdp5_kms->dev->dev; mdp5_kms 673 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(plane); mdp5_kms 674 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct device *dev = mdp5_kms->dev->dev; mdp5_kms 744 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, mdp5_kms 784 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); mdp5_kms 785 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); mdp5_kms 786 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); mdp5_kms 816 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, mdp5_kms 834 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), mdp5_kms 838 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), mdp5_kms 842 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), mdp5_kms 846 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), mdp5_kms 850 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), mdp5_kms 854 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), mdp5_kms 866 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), mdp5_kms 872 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), mdp5_kms 879 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); mdp5_kms 882 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write_pixel_ext(mdp5_kms, pipe, format, mdp5_kms 887 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), mdp5_kms 889 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), mdp5_kms 891 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), mdp5_kms 893 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), mdp5_kms 895 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), mdp5_kms 898 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), mdp5_kms 904 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c csc_enable(mdp5_kms, pipe, mdp5_kms 907 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c csc_disable(mdp5_kms, pipe); mdp5_kms 910 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c set_scanout_locked(mdp5_kms, pipe, fb); mdp5_kms 919 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_kms *mdp5_kms = get_kms(plane); mdp5_kms 1010 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, mdp5_kms 1016 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, mdp5_kms 32 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *get_kms(struct mdp5_smp *smp) mdp5_kms 121 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *mdp5_kms = get_kms(smp); mdp5_kms 122 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg); mdp5_kms 169 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *mdp5_kms = get_kms(smp); mdp5_kms 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct drm_device *dev = mdp5_kms->dev; mdp5_kms 259 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *mdp5_kms = get_kms(smp); mdp5_kms 265 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i), mdp5_kms 267 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i), mdp5_kms 274 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *mdp5_kms = get_kms(smp); mdp5_kms 277 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c for (i = 0; i < mdp5_kms->num_hwpipes; i++) { mdp5_kms 278 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; mdp5_kms 281 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), mdp5_kms 283 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), mdp5_kms 285 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), mdp5_kms 332 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_kms *mdp5_kms = get_kms(smp); mdp5_kms 342 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c drm_modeset_lock(&mdp5_kms->glob_state_lock, NULL); mdp5_kms 344 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c global_state = mdp5_get_existing_global_state(mdp5_kms); mdp5_kms 350 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c for (i = 0; i < mdp5_kms->num_hwpipes; i++) { mdp5_kms 351 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; mdp5_kms 372 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c drm_modeset_unlock(&mdp5_kms->glob_state_lock); mdp5_kms 380 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_block *cfg) mdp5_kms 393 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c smp->dev = mdp5_kms->dev; mdp5_kms 397 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c global_state = mdp5_get_existing_global_state(mdp5_kms); mdp5_kms 60 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h struct mdp5_kms; mdp5_kms 69 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,