mdp5_ctl_commit   147 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
mdp5_ctl_commit   168 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
mdp5_ctl_commit    98 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
mdp5_ctl_commit    72 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl_commit   213 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
mdp5_ctl_commit   247 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
mdp5_ctl_commit   516 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);