mdp5_ctl          137 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
mdp5_ctl          157 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
mdp5_ctl           90 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_ctl          139 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_ctl          224 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_ctl          867 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl;
mdp5_ctl         1124 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_ctl         1164 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
mdp5_ctl           52 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	struct mdp5_ctl *pair; /* Paired CTL to be flushed together */
mdp5_ctl           71 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	struct mdp5_ctl ctls[MAX_CTL];
mdp5_ctl           83 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data)
mdp5_ctl           92 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
mdp5_ctl          135 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
mdp5_ctl          168 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
mdp5_ctl          182 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static bool start_signal_needed(struct mdp5_ctl *ctl,
mdp5_ctl          207 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void send_start_signal(struct mdp5_ctl *ctl)
mdp5_ctl          224 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
mdp5_ctl          248 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl          329 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void mdp5_ctl_reset_blend_regs(struct mdp5_ctl *ctl)
mdp5_ctl          347 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl          470 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl          485 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
mdp5_ctl          526 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
mdp5_ctl          571 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
mdp5_ctl          576 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
mdp5_ctl          584 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
mdp5_ctl          623 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
mdp5_ctl          626 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	struct mdp5_ctl *ctl = NULL;
mdp5_ctl          667 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
mdp5_ctl          715 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
mdp5_ctl           27 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
mdp5_ctl           29 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
mdp5_ctl           33 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
mdp5_ctl           34 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
mdp5_ctl           37 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl           39 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
mdp5_ctl           55 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl           72 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
mdp5_ctl           74 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
mdp5_ctl          198 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
mdp5_ctl          234 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
mdp5_ctl          300 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
mdp5_ctl          405 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 				      struct mdp5_ctl *ctl)
mdp5_ctl          343 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 					     struct mdp5_ctl *ctl)
mdp5_ctl          384 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	struct mdp5_ctl *ctl;
mdp5_ctl          119 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	struct mdp5_ctl *ctl;
mdp5_ctl          166 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	struct mdp5_ctl *ctl;
mdp5_ctl          279 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
mdp5_ctl          291 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 		struct mdp5_interface *intf, struct mdp5_ctl *ctl);
mdp5_ctl          505 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		struct mdp5_ctl *ctl;