mdp4_write 93 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); mdp4_write 173 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); mdp4_write 184 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); mdp4_write 185 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); mdp4_write 186 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); mdp4_write 187 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); mdp4_write 211 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); mdp4_write 212 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); mdp4_write 213 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); mdp4_write 214 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); mdp4_write 215 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0); mdp4_write 216 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0); mdp4_write 217 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0); mdp4_write 218 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0); mdp4_write 240 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), mdp4_write 245 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); mdp4_write 246 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0); mdp4_write 247 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), mdp4_write 251 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); mdp4_write 252 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), mdp4_write 255 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0); mdp4_write 257 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); mdp4_write 260 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000); mdp4_write 261 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000); mdp4_write 262 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000); mdp4_write 374 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), mdp4_write 377 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova); mdp4_write 378 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), mdp4_write 383 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), mdp4_write 395 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma), mdp4_write 559 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config); mdp4_write 600 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); mdp4_write 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, mdp4_write 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period); mdp4_write 73 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); mdp4_write 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, mdp4_write 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); mdp4_write 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); mdp4_write 80 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); mdp4_write 81 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, mdp4_write 84 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL, mdp4_write 87 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew); mdp4_write 88 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0); mdp4_write 89 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0); mdp4_write 90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0); mdp4_write 101 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); mdp4_write 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 1); mdp4_write 119 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, mdp4_write 122 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); mdp4_write 123 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); mdp4_write 124 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, mdp4_write 127 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); mdp4_write 128 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); mdp4_write 129 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); mdp4_write 130 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, mdp4_write 133 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); mdp4_write 134 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); mdp4_write 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, mdp4_write 138 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); mdp4_write 139 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); mdp4_write 150 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); mdp4_write 205 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); mdp4_write 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR, mdp4_write 18 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); mdp4_write 39 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); mdp4_write 40 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); mdp4_write 63 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); mdp4_write 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); mdp4_write 47 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); mdp4_write 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); mdp4_write 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); mdp4_write 54 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); mdp4_write 68 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); mdp4_write 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); mdp4_write 71 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); mdp4_write 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); mdp4_write 73 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); mdp4_write 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); mdp4_write 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); mdp4_write 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); mdp4_write 81 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); mdp4_write 82 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); mdp4_write 83 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); mdp4_write 84 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); mdp4_write 85 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); mdp4_write 86 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); mdp4_write 89 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); mdp4_write 511 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); mdp4_write 512 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); mdp4_write 513 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); mdp4_write 121 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), mdp4_write 126 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), mdp4_write 130 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), mdp4_write 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), mdp4_write 139 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), mdp4_write 144 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), mdp4_write 148 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), mdp4_write 153 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), mdp4_write 175 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), mdp4_write 180 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), mdp4_write 184 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), mdp4_write 189 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), mdp4_write 193 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), mdp4_write 198 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), mdp4_write 244 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0); mdp4_write 245 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf); mdp4_write 246 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30); mdp4_write 251 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0); mdp4_write 290 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL, mdp4_write 293 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period); mdp4_write 294 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len); mdp4_write 295 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL, mdp4_write 298 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start); mdp4_write 299 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end); mdp4_write 300 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0); mdp4_write 301 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR, mdp4_write 304 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew); mdp4_write 305 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol); mdp4_write 306 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL, mdp4_write 309 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0); mdp4_write 310 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0); mdp4_write 325 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); mdp4_write 409 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1); mdp4_write 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); mdp4_write 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); mdp4_write 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); mdp4_write 90 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); mdp4_write 91 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); mdp4_write 145 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), mdp4_write 149 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), mdp4_write 153 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), mdp4_write 155 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), mdp4_write 157 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), mdp4_write 159 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe), mdp4_write 169 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i), mdp4_write 174 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i), mdp4_write 177 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i), mdp4_write 182 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i), mdp4_write 185 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i), mdp4_write 281 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe), mdp4_write 285 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe), mdp4_write 289 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe), mdp4_write 293 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe), mdp4_write 299 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe), mdp4_write 312 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe), mdp4_write 326 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode); mdp4_write 327 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step); mdp4_write 328 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step); mdp4_write 331 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),