mdp4_kms 61 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static struct mdp4_kms *get_kms(struct drm_crtc *crtc) mdp4_kms 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 93 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); mdp4_kms 118 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); mdp4_kms 119 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; mdp4_kms 152 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c static void setup_mixer(struct mdp4_kms *mdp4_kms) mdp4_kms 154 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct drm_mode_config *config = &mdp4_kms->dev->mode_config; mdp4_kms 173 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); mdp4_kms 179 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 184 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); mdp4_kms 185 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); mdp4_kms 186 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); mdp4_kms 187 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); mdp4_kms 211 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); mdp4_kms 212 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); mdp4_kms 213 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); mdp4_kms 214 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); mdp4_kms 215 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0); mdp4_kms 216 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0); mdp4_kms 217 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0); mdp4_kms 218 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0); mdp4_kms 221 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c setup_mixer(mdp4_kms); mdp4_kms 227 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 240 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), mdp4_kms 245 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); mdp4_kms 246 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0); mdp4_kms 247 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), mdp4_kms 251 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); mdp4_kms 252 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), mdp4_kms 255 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0); mdp4_kms 257 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); mdp4_kms 260 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000); mdp4_kms 261 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000); mdp4_kms 262 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000); mdp4_kms 270 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 280 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); mdp4_kms 281 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_disable(mdp4_kms); mdp4_kms 290 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 297 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_enable(mdp4_kms); mdp4_kms 302 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); mdp4_kms 357 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 358 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; mdp4_kms 374 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), mdp4_kms 377 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova); mdp4_kms 378 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), mdp4_kms 383 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), mdp4_kms 384 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_kms->blank_cursor_iova); mdp4_kms 395 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma), mdp4_kms 407 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 408 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; mdp4_kms 528 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 536 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) & mdp4_kms 557 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 559 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config); mdp4_kms 566 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(crtc); mdp4_kms 569 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL); mdp4_kms 600 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); mdp4_kms 21 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c static struct mdp4_kms *get_kms(struct drm_encoder *encoder) mdp4_kms 43 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, mdp4_kms 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period); mdp4_kms 73 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); mdp4_kms 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, mdp4_kms 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); mdp4_kms 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); mdp4_kms 80 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); mdp4_kms 81 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, mdp4_kms 84 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL, mdp4_kms 87 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew); mdp4_kms 88 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0); mdp4_kms 89 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0); mdp4_kms 90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0); mdp4_kms 96 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 101 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); mdp4_kms 111 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC); mdp4_kms 119 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 1); mdp4_kms 22 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c static struct mdp4_kms *get_kms(struct drm_encoder *encoder) mdp4_kms 89 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 119 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, mdp4_kms 122 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); mdp4_kms 123 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); mdp4_kms 124 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, mdp4_kms 127 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); mdp4_kms 128 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); mdp4_kms 129 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); mdp4_kms 130 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, mdp4_kms 133 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); mdp4_kms 134 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); mdp4_kms 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, mdp4_kms 138 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); mdp4_kms 139 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); mdp4_kms 145 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 150 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); mdp4_kms 160 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); mdp4_kms 174 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 205 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); mdp4_kms 23 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = container_of(irq, struct mdp4_kms, error_handler); mdp4_kms 30 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct drm_printer p = drm_info_printer(mdp4_kms->dev->dev); mdp4_kms 31 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c drm_state_dump(mdp4_kms->dev, &p); mdp4_kms 37 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 38 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_enable(mdp4_kms); mdp4_kms 39 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); mdp4_kms 40 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); mdp4_kms 41 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_disable(mdp4_kms); mdp4_kms 47 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); mdp4_kms 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp_irq *error_handler = &mdp4_kms->error_handler; mdp4_kms 61 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 62 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_enable(mdp4_kms); mdp4_kms 63 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); mdp4_kms 64 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_disable(mdp4_kms); mdp4_kms 70 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); mdp4_kms 71 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct drm_device *dev = mdp4_kms->dev; mdp4_kms 76 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c enable = mdp4_read(mdp4_kms, REG_MDP4_INTR_ENABLE); mdp4_kms 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS) & enable; mdp4_kms 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); mdp4_kms 93 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 95 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_enable(mdp4_kms); mdp4_kms 98 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_disable(mdp4_kms); mdp4_kms 105 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 107 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_enable(mdp4_kms); mdp4_kms 110 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_disable(mdp4_kms); mdp4_kms 20 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 21 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct drm_device *dev = mdp4_kms->dev; mdp4_kms 28 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_enable(mdp4_kms); mdp4_kms 29 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); mdp4_kms 30 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_disable(mdp4_kms); mdp4_kms 44 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->rev = minor; mdp4_kms 46 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->rev > 1) { mdp4_kms 47 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); mdp4_kms 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); mdp4_kms 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); mdp4_kms 54 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); mdp4_kms 56 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk = clk_get_rate(mdp4_kms->clk); mdp4_kms 58 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { mdp4_kms 68 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); mdp4_kms 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); mdp4_kms 71 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); mdp4_kms 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); mdp4_kms 73 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); mdp4_kms 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); mdp4_kms 76 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->rev >= 2) mdp4_kms 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); mdp4_kms 78 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); mdp4_kms 81 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); mdp4_kms 82 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); mdp4_kms 83 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); mdp4_kms 84 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); mdp4_kms 85 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); mdp4_kms 86 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); mdp4_kms 88 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->rev > 1) mdp4_kms 89 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); mdp4_kms 101 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 102 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_enable(mdp4_kms); mdp4_kms 107 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 108 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_disable(mdp4_kms); mdp4_kms 129 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 132 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask) mdp4_kms 138 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 142 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask) mdp4_kms 166 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); mdp4_kms 167 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct device *dev = mdp4_kms->dev->dev; mdp4_kms 170 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->blank_cursor_iova) mdp4_kms 171 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); mdp4_kms 172 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo); mdp4_kms 180 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->rpm_enabled) mdp4_kms 183 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c kfree(mdp4_kms); mdp4_kms 208 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c int mdp4_disable(struct mdp4_kms *mdp4_kms) mdp4_kms 212 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_disable_unprepare(mdp4_kms->clk); mdp4_kms 213 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->pclk) mdp4_kms 214 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_disable_unprepare(mdp4_kms->pclk); mdp4_kms 215 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->lut_clk) mdp4_kms 216 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_disable_unprepare(mdp4_kms->lut_clk); mdp4_kms 217 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->axi_clk) mdp4_kms 218 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_disable_unprepare(mdp4_kms->axi_clk); mdp4_kms 223 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c int mdp4_enable(struct mdp4_kms *mdp4_kms) mdp4_kms 227 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_prepare_enable(mdp4_kms->clk); mdp4_kms 228 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->pclk) mdp4_kms 229 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_prepare_enable(mdp4_kms->pclk); mdp4_kms 230 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->lut_clk) mdp4_kms 231 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_prepare_enable(mdp4_kms->lut_clk); mdp4_kms 232 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->axi_clk) mdp4_kms 233 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_prepare_enable(mdp4_kms->axi_clk); mdp4_kms 239 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, mdp4_kms 242 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct drm_device *dev = mdp4_kms->dev; mdp4_kms 336 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c static int modeset_init(struct mdp4_kms *mdp4_kms) mdp4_kms 338 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct drm_device *dev = mdp4_kms->dev; mdp4_kms 405 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); mdp4_kms 423 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct mdp4_kms *mdp4_kms; mdp4_kms 428 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); mdp4_kms 429 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (!mdp4_kms) { mdp4_kms 435 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp_kms_init(&mdp4_kms->base, &kms_funcs); mdp4_kms 437 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c kms = &mdp4_kms->base.base; mdp4_kms 439 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->dev = dev; mdp4_kms 441 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4"); mdp4_kms 442 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->mmio)) { mdp4_kms 443 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = PTR_ERR(mdp4_kms->mmio); mdp4_kms 460 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); mdp4_kms 461 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->vdd)) mdp4_kms 462 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->vdd = NULL; mdp4_kms 464 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->vdd) { mdp4_kms 465 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = regulator_enable(mdp4_kms->vdd); mdp4_kms 472 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); mdp4_kms 473 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->clk)) { mdp4_kms 475 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = PTR_ERR(mdp4_kms->clk); mdp4_kms 479 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); mdp4_kms 480 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->pclk)) mdp4_kms 481 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->pclk = NULL; mdp4_kms 483 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->rev >= 2) { mdp4_kms 484 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); mdp4_kms 485 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->lut_clk)) { mdp4_kms 487 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = PTR_ERR(mdp4_kms->lut_clk); mdp4_kms 492 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); mdp4_kms 493 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->axi_clk)) { mdp4_kms 495 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = PTR_ERR(mdp4_kms->axi_clk); mdp4_kms 499 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_set_rate(mdp4_kms->clk, config->max_clk); mdp4_kms 500 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (mdp4_kms->lut_clk) mdp4_kms 501 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c clk_set_rate(mdp4_kms->lut_clk, config->max_clk); mdp4_kms 504 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->rpm_enabled = true; mdp4_kms 510 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_enable(mdp4_kms); mdp4_kms 511 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); mdp4_kms 512 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); mdp4_kms 513 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); mdp4_kms 514 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_disable(mdp4_kms); mdp4_kms 537 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = modeset_init(mdp4_kms); mdp4_kms 543 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); mdp4_kms 544 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c if (IS_ERR(mdp4_kms->blank_cursor_bo)) { mdp4_kms 545 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = PTR_ERR(mdp4_kms->blank_cursor_bo); mdp4_kms 547 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp4_kms->blank_cursor_bo = NULL; mdp4_kms 551 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, mdp4_kms 552 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c &mdp4_kms->blank_cursor_iova); mdp4_kms 43 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) mdp4_kms 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) mdp4_kms 53 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h msm_writel(data, mdp4_kms->mmio + reg); mdp4_kms 56 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) mdp4_kms 58 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h return msm_readl(mdp4_kms->mmio + reg); mdp4_kms 155 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h int mdp4_disable(struct mdp4_kms *mdp4_kms); mdp4_kms 156 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h int mdp4_enable(struct mdp4_kms *mdp4_kms); mdp4_kms 27 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c static struct mdp4_kms *get_kms(struct drm_encoder *encoder) mdp4_kms 103 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 121 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), mdp4_kms 126 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), mdp4_kms 130 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), mdp4_kms 135 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), mdp4_kms 139 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), mdp4_kms 144 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), mdp4_kms 148 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), mdp4_kms 153 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), mdp4_kms 175 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), mdp4_kms 180 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), mdp4_kms 184 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), mdp4_kms 189 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), mdp4_kms 193 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), mdp4_kms 198 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), mdp4_kms 244 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0); mdp4_kms 245 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf); mdp4_kms 246 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30); mdp4_kms 251 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0); mdp4_kms 260 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 290 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL, mdp4_kms 293 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period); mdp4_kms 294 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len); mdp4_kms 295 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL, mdp4_kms 298 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start); mdp4_kms 299 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end); mdp4_kms 300 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0); mdp4_kms 301 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR, mdp4_kms 304 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew); mdp4_kms 305 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol); mdp4_kms 306 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL, mdp4_kms 309 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0); mdp4_kms 310 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0); mdp4_kms 318 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 325 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); mdp4_kms 341 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC); mdp4_kms 362 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct mdp4_kms *mdp4_kms = get_kms(encoder); mdp4_kms 409 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1); mdp4_kms 19 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll) mdp4_kms 60 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); mdp4_kms 69 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); mdp4_kms 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); mdp4_kms 74 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); mdp4_kms 77 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED)) mdp4_kms 86 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); mdp4_kms 90 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); mdp4_kms 91 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); mdp4_kms 53 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c static struct mdp4_kms *get_kms(struct drm_plane *plane) mdp4_kms 96 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct mdp4_kms *mdp4_kms = get_kms(plane); mdp4_kms 97 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct msm_kms *kms = &mdp4_kms->base.base; mdp4_kms 141 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct mdp4_kms *mdp4_kms = get_kms(plane); mdp4_kms 142 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct msm_kms *kms = &mdp4_kms->base.base; mdp4_kms 145 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), mdp4_kms 149 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), mdp4_kms 153 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), mdp4_kms 155 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), mdp4_kms 157 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), mdp4_kms 159 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe), mdp4_kms 163 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms, mdp4_kms 169 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i), mdp4_kms 174 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i), mdp4_kms 177 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i), mdp4_kms 182 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i), mdp4_kms 185 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i), mdp4_kms 201 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct mdp4_kms *mdp4_kms = get_kms(plane); mdp4_kms 281 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe), mdp4_kms 285 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe), mdp4_kms 289 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe), mdp4_kms 293 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe), mdp4_kms 299 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe), mdp4_kms 312 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe), mdp4_kms 323 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write_csc_config(mdp4_kms, pipe, csc); mdp4_kms 326 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode); mdp4_kms 327 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step); mdp4_kms 328 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step); mdp4_kms 331 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),