mdp4_dma          447 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t __offset_DMA(enum mdp4_dma idx)
mdp4_dma          456 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
mdp4_dma          458 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
mdp4_dma          487 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
mdp4_dma          501 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
mdp4_dma          503 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
mdp4_dma          505 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
mdp4_dma          519 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
mdp4_dma          533 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
mdp4_dma          535 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
mdp4_dma          549 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
mdp4_dma          559 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
mdp4_dma          561 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
mdp4_dma          563 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
mdp4_dma          565 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
mdp4_dma          567 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
mdp4_dma          570 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          572 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          574 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          576 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          578 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          580 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          582 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          584 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          586 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma          588 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
mdp4_dma           20 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	enum mdp4_dma dma;
mdp4_dma          228 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	enum mdp4_dma dma = mdp4_crtc->dma;
mdp4_dma          359 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	enum mdp4_dma dma = mdp4_crtc->dma;
mdp4_dma          619 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		enum mdp4_dma dma_id)
mdp4_dma          349 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c 	static const enum mdp4_dma mdp4_crtcs[] = {
mdp4_dma           81 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t dma2irq(enum mdp4_dma dma)
mdp4_dma           91 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t dma2err(enum mdp4_dma dma)
mdp4_dma          195 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h 		enum mdp4_dma dma_id);