MC_WR_GRP_OTH__UVD_MASK 10042 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L
MC_WR_GRP_OTH__UVD_MASK 2957 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
MC_WR_GRP_OTH__UVD_MASK 3561 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
MC_WR_GRP_OTH__UVD_MASK 3963 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
MC_WR_GRP_OTH__UVD_MASK 3805 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_WR_GRP_OTH__UVD_MASK 0xf00000