MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 9675 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x00000004
MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 7202 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 8116 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4