MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 9661 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x00000004
MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 7164 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 8078 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4