MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 9653 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x00000000
MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 7232 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 8146 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0