MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 9645 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x00000018
MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 7158 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 8072 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18