MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 9641 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x00000008
MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 7154 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 8068 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8