MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 9635 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x00000010
MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 7148 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 8062 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10