MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 9596 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000L
MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 6597 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 7511 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000