MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 9594 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0x0f000000L
MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 6595 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 7509 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000