MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 9543 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018
MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 6570 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 7484 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18