MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 9515 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x00000008
MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 6556 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 7470 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8