MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 9510 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0x0000000fL
MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 6551 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 7465 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf