MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 9493 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x00000006
MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 9058 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 9970 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6