MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 9468 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0x00000f00L
MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 6815 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 7729 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00