MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 9242 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0x00ff0000L
MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 9271 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 10183 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000