MC_SEQ_TCG_CNTL__RESET_MASK 8846 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_TCG_CNTL__RESET_MASK 0x00000001L
MC_SEQ_TCG_CNTL__RESET_MASK 9149 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
MC_SEQ_TCG_CNTL__RESET_MASK 10061 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_TCG_CNTL__RESET_MASK 0x1