MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 8832 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x00000004L
MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 9153 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 10065 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4