MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 8771 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x00000007
MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 8638 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 9552 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7