MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 8769 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x00000006
MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 8636 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 9550 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6