MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 8737 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x00000002
MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 8628 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 9542 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2