MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 8133 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0x0000000c
MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 8702 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 9614 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc