MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 13943 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 14857 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000