MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 13933 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 14847 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1