MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 8113 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x00000002
MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 7866 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 8780 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2