MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 8112 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0x0000000cL
MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 7865 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 8779 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc