MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 8101 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x00000006
MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 7870 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 8784 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6