MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 8100 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0x000000c0L
MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 7869 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 8783 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0