MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 7885 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 8799 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000