MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 7967 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x00000017
MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 6354 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 7268 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17