MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 7965 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x00000016
MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 6352 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 7266 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16