MC_SEQ_CNTL_2__DRST_PU_MASK 6341 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
MC_SEQ_CNTL_2__DRST_PU_MASK 7255 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10