MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 7865 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0x0000000f
MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 8838 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 9750 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf