MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 7785 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0x0000000f
MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 8854 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 9766 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf