MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 7691 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d
MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 2816 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 3398 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 3784 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 3626 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd