MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 3360 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 3358 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 1380 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 3584 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0