MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 3336 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 3334 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 1356 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 3560 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0