MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 3310 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 3308 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 1330 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 3534 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10