MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 3286 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 3284 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 1306 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 3510 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10