MC_PHY_TIMING_D1__TXC0_DLY_MASK 7398 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x00070000L
MC_PHY_TIMING_D1__TXC0_DLY_MASK 9321 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
MC_PHY_TIMING_D1__TXC0_DLY_MASK 10233 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000