MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 2563 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008
MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 6808 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 7722 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8