MC_DLB_MISCCTRL2__STATUS_SEL_MASK 14115 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
MC_DLB_MISCCTRL2__STATUS_SEL_MASK 15029 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000