MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT  855 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d
MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT  752 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT  810 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT  856 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT  854 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd