MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT  851 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f
MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT  756 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT  814 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT  860 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT  858 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf